1. Field of the Invention
The present invention is generally related to testing systems for integrated circuits. It is also related to systems for parallel testing integrated circuit chips. It is more specifically related to an in-transit test system for testing application specific integrated circuits (ASICs).
2. Description of the Related Art
Application specific integrated circuits (ASICs) are customized circuits which are generally produced in limited numbers. Testing such circuits present problems because of the unique role each different ASIC batch is designed to perform.
More specifically, the design for an ASIC is usually supplied to a semiconductor foundry which manufactures individual chip packages. The chip packages are then to shipped to a different location such as a module build house, which packages the chips. The packaged chips are then shipped to a different location, usually back to the original foundry, to be tested. After being tested the non-defective chips are shipped to a different location such as the system house for system assembly.
The extra processing required to test the ASIC adds substantially to the cost of the product being produced and increases the time that it takes to bring a product to market. Further, conventional testing mechanisms generally comprise large multi-million dollar testing operations which are capable of performing the varied testing that the uniquely functioning ASICs require. Therefore, there is a need to reduce the time and resources devoted to testing ASIC products.